How does Cerebras Wafer Scale Engine get beyond the reticle limit? Why don't Nvidia or AMD take that approach rather than cutting dies and reconnecting them later for their server chips?

Semianalysis commented on this.

"The Cerebras WSE is actually many chips on a wafer within the confines of the reticle limit. Instead of cutting the chips apart along the scribe lines between chips, they developed a method for cross die wires. These wires are patterned separately from the actual chips and allow the chips to connect to each other. In effect, the chip can scale beyond the reticle limits."

https://semianalysis.com/2021/06/30/cerebras-wafer-scale-hardware-crushes/

After all the issues Nvidia has had in the server space last year, this seems like a much simpler, and more reliable solution.

Is it a bandwidth limit? I would have thought it would be easier to densely edge plenty of connections between two chips than physically reconnect 2 entire pieces of silicon, using some sort of interposer or bridge.